Maximum IR-drop in On-Chip Power Distribution Networks of Wire-Bonded Integrated Circuits

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Title:	Maximum IR-drop in On-Chip Power Distribution Networks of Wire-Bonded Integrated Circuits
Author:	Rius Vázquez, José; Aguareles Carrero, María
Other authors:	Universitat Politècnica de Catalunya. Departament de Matemàtica Aplicada I; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. EGSA - Equacions Diferencials, Geometria, Sistemes Dinàmics i de Control, i Aplicacions; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
Abstract:	A compact IR-drop model for on-chip power distribution networks in wire-bonded ICs is presented. Chip dimensions, metal coverage and piecewise distribution of the IC consumption are taken into account to obtain closed form expressions for the maximum IR-drop as well as its place. Comparison with simulations shows an error as small as 2% in most the cases.
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica -Circuits integrats a molt gran escala
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Conference Object
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