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Title:
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Impact of positive bias temperature instability (PBTI)
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Author:
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Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
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Abstract:
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Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Hardware
-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Memory management (Computer science)
-Device degradation
-Memòria -- Gestió -- Informàtica
-Components electrònics -- Proves |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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