This paper presents an improved modeling of the effect of random mismatch and current source transient switching behavior on the performance of current-steering CMOS digital-toanalog converters (DACs). The work considers two current source cell topologies, namely a simple cell and a cascoded cell, obtaining the relation of transistors design parameters to the static and dynamic models. On the one hand, a mismatching statistical analysis is applied to all the transistors of the current source circuit, which allows to define design expressions relating the circuit parameters to the DAC specifications without the need of arbitrary design margins or Monte Carlo simulations. On the other hand, improved analysis of the current source switching characteristics provides a more realistic modeling of the relation between transistors sizes and output current settling time. By including these two improved models into the usual design procedure, circuit sizing for optimum settling time and proper static behavior can be obtained analytically, reverting in smaller current source area, and, hence, in an overall DAC area reduction.