Título:
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Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption
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Autor/a:
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Barajas Ojeda, Enrique; Mateo Peña, Diego; González Jiménez, José Luis
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
Abstract:
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This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal -Logic design -Delay lock loops -DLL behavioural modelling -Jitter optimisation -Processament del senyal |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Objeto de conferencia |
Editor:
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IEEE Computer Society Publications
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Compartir:
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