Título:
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DLL's behavioral modeling for power consumption and jitter fast optimization
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Autor/a:
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Barajas Ojeda, Enrique; Mateo Peña, Diego; González Jiménez, José Luis
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
Abstract:
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This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter versus the power consumption is studied. |
Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal -Delay lock loops -Logic design -Jitter -DLL |
Derechos:
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Tipo de documento:
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Artículo - Versión presentada Objeto de conferencia |
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