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Título:
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Gate leakage impact on full open defects in interconnect lines
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Autor/a:
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Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
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Abstract:
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An Interconnect full open defect breaks the connection
between the driver and the gate terminals of downstream transistors,
generating a floating line. The behavior of floating lines is
known to depend on several factors, namely parasitic capacitances
to neighboring structures, transistor capacitances of downstream
gate(s) and trapped charges. For nanometer CMOS technologies,
the reduction of oxide thickness leads to a significant increase in
gate tunneling leakage. This new phenomenon influences the behavior
of circuits with interconnect full open defects. Floating lines
can no longer be considered electrically isolated and are subjected
to transient evolutions, reaching a steady state determined by the
technology, downstream interconnect and gate(s) topology. The occurrence
of such defects and the impact of gate tunneling leakage
are expected to increase in the future. In this work, interconnect
full open defects affecting nanometer CMOS technologies are analyzed
and the defective logic response of downstream gates after
reaching the steady state is predicted. Experimental evidence of
this behavior is presented for circuits belonging to a 180 nm and
a 65 nm CMOS technologies. Technology trends show that the impact
of gate leakage currents is expected to increase in future technologies. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica
-Metal oxide semiconductors, Complementary
-Metall-òxid-semiconductors complementaris |
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Derechos:
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Tipo de documento:
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Artículo - Versión presentada
Artículo |
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