Title:
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A new probabilistic design methodology of nanoscale digital circuits
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Author:
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García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
Abstract:
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The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design.
The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics -Integrated circuits -- Design and construction -Nanoelectromechanical systems -Nanoscale digital circuits -Circuits integrats -Nanotecnologia -- Aplicacions |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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IEEE Press. Institute of Electrical and Electronics Engineers
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