|
Title:
|
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
|
|
Author:
|
Jaksic, Zoran; Canal Corretger, Ramon
|
|
Other authors:
|
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
|
Abstract:
|
In this paper, we
pr
esent the dynamic 3T memory
cell for future 10nm tri-gate FinFETs as a potential replacement
for classical 6T SRAM cell for implementation in high speed
cache memories. We investigate read access time, retention time,
and static power consumption of the cell when it is exposed
to the effects of process and environmental variations. Process
variations are extracted from the ITRS predictions and they are
modeled at device level. For simulation, we use 10nm SOI tri-gate
FinFET BSIM-CMG model card developed by the University
of Glasgow, Device Modeling Group. When compared to the
classical 6T SRAM, 3T cell has 40% smaller area, leakage is
reduced up to 14 times while access time is approximately the
same. In order to achieve higher retention times, we propose
several cell extensions which, at the same time, enable post-
fabrication/run-time adaptability. |
|
Abstract:
|
Peer Reviewed |
|
Subject(s):
|
-Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
-Àrees temàtiques de la UPC::Informàtica::Hardware
-Semiconductor storage devices
-Ordinadors -- Memòries semiconductores |
|
Rights:
|
|
|
Document type:
|
Article - Published version
Conference Object |
|
Published by:
|
IEEE Computer Society Publications
|
|
Share:
|
|
