BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

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Title:	BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
Author:	Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
Abstract:	built-in self test integrated circuit testing three-dimensional integrated circuits
Abstract:	Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica -Integrated circuits -Three-dimensional integrated circuits -built-in self test integrated circuit testing three-dimensional integrated circuits -Circuits integrats
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Document type:	Article - Published version Conference Object
Published by:	Institute of Electrical and Electronics Engineers (IEEE)
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