Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems

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Title:	Hardware-efficient implementation of a femtocell/macrocell interference-mitigation technique for high-performance LTE-based systems
Author:	Font Bach, Oriol; Bartzoudis, Nikolaos; Pascual Iserte, Antonio; Payaró Llisterri, Miquel
Other authors:	Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions; Universitat Politècnica de Catalunya. SPCOM - Grup de Recerca de Processament del Senyal i Comunicacions
Abstract:	This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica::Comunicacions mòbils -Long-Term Evolution (Telecommunications) -Interference (Sound) -Synchronization -Field programmable gate arrays -Finite impulse response filters -Interference -OFDM -Real-time systems -Resource management -Synchronization -Long-term evolution (Telecomunicacions) -Sincronització -Interferències
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Document type:	Article - Published version Conference Object
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