Title:
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APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation
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Author:
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Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance- Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-efficient and smaller cells enhanced with extra cache lines set up in an adapted victim cache to still enable strong performance guarantees. APPLE caches are proven to largely outperform existing solutions in terms of energy and area efficiency. |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Cache memory -Cache -Faults -Low energy -Predictable performance -Memòria ràpida de treball (Informàtica) |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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