Título:
|
Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
|
Autor/a:
|
Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Mauricio Ferré, Juan
|
Otros autores:
|
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
Abstract:
|
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE) |
Abstract:
|
Peer Reviewed |
Materia(s):
|
-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Nanoelectronics -Lithography -Design for manufacturability -Lithography hotspots -Yield estimation -Layout design -Nanoelectrònica -Litografia |
Derechos:
|
|
Tipo de documento:
|
Artículo - Versión presentada Artículo |
Compartir:
|
|