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Defeating simple power analysis attacks in cache memories
Neagu, Madalin; Manich Bou, Salvador; Miclea, Liviu
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). However, side channel attacks like the Simple Power Analysis (SPA) can still circumvent this protection. Error detection and correction codes (EDC/ECC) are employed in memories to increase reliability, but they can also be used to increase the security. This paper proposes to boost the IST with an ECC code in order to create a cache resistant against SPA-attacks. The redundancy provided by the ECC code is used to create confusion by enlarging the search space where the hacker has to look for to find the secret keys.
-Àrees temàtiques de la UPC::Informàtica
-Cache memory -- Security measures
-Data encryption (Computer science)
-Data scrambling
-cache memories
-cold-boot attack
-self-healing memories
-simple power analysis
-side channel attack.
-Memòria cau -- Mesures de seguretat
-Encriptació de dades (Informàtica)
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Artículo - Versión publicada
Objeto de conferencia
Institute of Electrical and Electronics Engineers (IEEE)
         

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