RTL synthesis: From logic synthesis to automatic pipelining

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Título:	RTL synthesis: From logic synthesis to automatic pipelining
Autor/a:	Cortadella, Jordi; Galcerán Oms, Marc; Kishinevsky, Mike; Sapatnekar, Sachin S.
Otros autores:	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
Abstract:	Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.
Abstract:	Peer Reviewed
Materia(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics -Semiconductor industry -Logic design -Design automation -Logic synthesis -High-level synthesis -Architectural pipelining -Timing elasticity -Semiconductors -- Indústria i comerç -Estructura lògica
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Tipo de documento:	Artículo - Versión presentada Artículo
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Galcerán Oms, Marc; Cortadella, Jordi; Kishinevsky, Mike

Bufistov, Dmitry; Cortadella, Jordi; Galcerán Oms, Marc; Julvez Bueno, Jorge Emilio; Kishinevsky, Mike

Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella, Jordi

Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S.

Bufistov, Dmitry; Cortadella, Jordi; Kishinevsky, Michael; Sapatnekar, Sachin S.

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