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Título:
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Ring oscillator clocks and margins
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Autor/a:
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Cortadella, Jordi; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin
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Otros autores:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
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Abstract:
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How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
-Oscillators, Electric
-Asynchronous circuits
-Clocks
-Delay lines
-Phase locked loops
-Ring oscillator clocks
-Delay lines
-EDA machinery
-Timing analysis
-PLL
-Clock generator
-Oscil·ladors elèctrics
-Circuits asíncrons |
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Derechos:
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Tipo de documento:
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Artículo - Versión presentada
Objeto de conferencia |
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Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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Compartir:
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