|
Title:
|
Charge trapping control in MOS capacitors
|
|
Author:
|
Domínguez Pumar, Manuel; Bheesayagari, Chenna Reddy; Gorreta Mariné, Sergio; López Rodríguez, Gema; Martín García, Isidro; Blokhina, Elena; Pons Nin, Joan
|
|
Other authors:
|
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions; Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies |
|
Abstract:
|
This paper presents an active control of C-V characteristic for MOS capacitors based on Sliding Mode control and sigma-delta-modulation. The capacitance of the device at a certain voltage is measured periodically and adequate voltage excitations are generated by a feedback loop to place the C-V curve at the desired target position. Experimental results are presented for a n-type c-Si MOS capacitor made with silicon dioxide. It is shown that with this approach it is possible to shift horizontally the C-V curve to the desired operation point. A physical analysis is also presented to explain how the C-V horizontal displacements can be linked to charge trapping in the bulk of the oxide and/or in the silicon-oxide interface. Finally, design criteria are provided for tuning the main parameters of the sliding mode controller. |
|
Abstract:
|
Peer Reviewed |
|
Subject(s):
|
-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
-Metal oxide semiconductors
-Capacitance-voltage characteristics
-Voltage measurement
-Capacitance
-Charge carrier processes
-Capacitance measurement
-MOS capacitors
-Feedback loop
-Metall-òxid-semiconductors |
|
Rights:
|
|
|
Document type:
|
Article - Submitted version
Article |
|
Published by:
|
Institute of Electrical and Electronics Engineers (IEEE)
|
|
Share:
|
|
