Título:
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Explaining dynamic cache partitioning speed ups
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Autor/a:
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Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Microprocessors -Cache memory -Microprocessor chips -Cache storage -Microprocessadors -Memòria ràpida de treball (Informàtica) |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Artículo |
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