Título:
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pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
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Autor/a:
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Slijepcevic, Mladen; Fernández, Mikel; Hernández, Carles; Abella, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention in the access to the NoC among running tasks. Probabilistic Timing Analysis (PTA) is a powerful approach to derive WCET estimates on relatively complex processors. However, so far it has only been tested on small multicores comprising an on-chip bus as communication means, which intrinsically does not scale to high core counts. In this paper we propose pTNoC, a new tree-based NoC design compatible with PTA requirements and delivering scalability towards medium/large core counts. pTNoC provides tight WCET estimates by means of asymmetric bandwidth guarantees for mixed-criticality systems with negligible impact on average performance. Finally, our implementation results show the reduced area and power costs of the pTNoC. |
Abstract:
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The research leading to these results has received funding from the European Community’s Seventh Framework Programme [FP7/2007-2013] under the PROXIMA Project
(www.proxima-project.eu), grant agreement no 611085. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Mladen Slijepcevic is funded by the Obra Social Fundación la Caixa under grant Doctorado “la Caixa” - Severo Ochoa. Carles
Hern´andez is jointly funded by the Spanish Ministry of Economy and Competitiveness (MINECO) and FEDER funds through grant TIN2014-60404-JIN. Jaume Abella has been
partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Networks on a chip -Multiprocessors -Multicore processing -Probabilistic logic -Timing -Program processors -Aerospace electronics -Bandwidth -Real-time systems -Ordinadors immersos, Sistemes d' -Multiprocessadors |
Derechos:
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Tipo de documento:
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Artículo - Versión presentada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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