Power evaluation is an important issue in new proposal chip level architectures due to the big amount of power is dissipated as head and chips have limited head dissipation capacity. The evaluation shown in this technical report don’t use any low-power techniques; main goal of this work is known the upper limit consumption of the Multi-State Processor’s RF design, power optimization is a work to be making through the steps of design flow. Logic design has being performed at transistor level using SPICE simulator, once the basic structures of RF took shape power consumption was analyzed, the source of technology parameters used in this work is Predictive Technology Models (PMT) provided by the Nanoscale Integration and Modeling Group at UC Berkeley [9].