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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades |
dc.contributor.author | Soto, Javier |
dc.contributor.author | Moreno Aróstegui, Juan Manuel |
dc.contributor.author | Cabestany Moncusí, Joan |
dc.date | 2011 |
dc.identifier.citation | Soto, J.; Moreno, J.; Cabestany, J. Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities. A: International Work-Conference on Artificial Neural Networks. "11th International Work-Conference on Artificial Neural Networks". Torremolinos: Springer Verlag, 2011, p. 557-564. |
dc.identifier.citation | 0302-9743 |
dc.identifier.citation | 10.1007/978-3-642-21498-1_70 |
dc.identifier.uri | http://hdl.handle.net/2117/13973 |
dc.language.iso | eng |
dc.publisher | Springer Verlag |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture |
dc.subject | Arquitectura d'ordinadors |
dc.title | Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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