A selective logging mechanism for hardware transactional memory systems

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.author	Lupon Navazo, Marc
dc.contributor.author	Magklis, Grigorios
dc.contributor.author	González Colás, Antonio María
dc.date	2011-09-19
dc.identifier.citation	Lupon, M.; Magklis, G.; González, A. "A selective logging mechanism for hardware transactional memory systems". 2011.
dc.identifier.uri	http://hdl.handle.net/2117/15009
dc.language.iso	eng
dc.relation	UPC-DAC-RR-ARCO-2011-5
dc.relation	http://www.ac.upc.edu/app/research-reports/html/2011/44/SelectiveLogging.pdf
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Transactional memory
dc.subject	Memòria transaccional
dc.title	A selective logging mechanism for hardware transactional memory systems
dc.type	info:eu-repo/semantics/submittedVersion
dc.type	info:eu-repo/semantics/report
dc.description.abstract	Log-based Hardware Transactional Memory (HTM) systems offer an elegant solution to handle speculative data that overflow transactional L1 caches. By keeping the pre-transactional values on a software-resident log, speculative values can be safely moved across the memory hierarchy, without requiring expensive searches on L1 misses or commits.