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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.contributor.author | Champac Vilela, Víctor Hugo |
dc.contributor.author | Avendaño, Victor |
dc.contributor.author | Figueras Pàmies, Joan |
dc.date | 2010-02 |
dc.identifier.citation | Champac, V.; Avendaño, V.; Figueras, J. Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. "IEEE transactions on very large scale integration (VLSI) systems", Febrer 2010, vol. 18, núm. 2, p. 256-269. |
dc.identifier.citation | 1063-8210 |
dc.identifier.citation | 10.1109/TVLSI.2008.2010398 |
dc.identifier.uri | http://hdl.handle.net/2117/7805 |
dc.language.iso | eng |
dc.relation | http://sciencestage.com/d/5625290/built-in-sensor-for-signal-integrity-faults-in-digital-interconnect-signals.html |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Digital integrated circuits |
dc.subject | Integrated circuits--Design |
dc.subject | Integrated circuits--Testing |
dc.subject | Circuits integrats digitals |
dc.subject | Circuits integrats digitals -- Disseny |
dc.subject | Circuits integrats digitals -- Proves |
dc.title | Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract |