Comunicació presentada en la 34th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '09), celebrada els dies 19, 20, 21, 22, 23 i 24 d’abril de 2009 a Taipei, (Taiwan), organitzada per l’Institute of Electrical and Electronics Engineers (IEEE).

A systolic array to implement lattice-reduction-aided linear/ndetection is proposed for a MIMO receiver. The lattice reduction/nalgorithm and the ensuing linear detections are operated in the same array, which can be hardware-efficient. All-swap lattice reduction algorithm (ASLR) is considered for the systolic design./nASLR is a variant of the LLL algorithm, which processes all lattice basis vectors within one iteration. Lattice-reduction-aided linear detection based on ASLR and LLL algorithms have very similar/nbit-error-rate performance, while ASLR is more time efficient in/nthe systolic array, especially for systems with a large number of/nantennas.

The work of N.C. Wang was partially supported by National Science Council, Taiwan. (TMS-094-2-A-002).