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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Torrents Lapuerta, Martí |
dc.contributor.author | Martinez Morais, Raul |
dc.contributor.author | Molina Clemente, Carlos |
dc.date | 2014-06-01 |
dc.identifier.citation | Torrents, M.; Martinez Morais, Raul; Molina, C. Network aware performance evaluation of prefetching techniques in CMPs. "Simulation modelling practice and theory", 01 Juny 2014, vol. 45, p. 1-17. |
dc.identifier.citation | 1569-190X |
dc.identifier.citation | 10.1016/j.simpat.2014.03.005 |
dc.identifier.uri | http://hdl.handle.net/2117/23050 |
dc.language.iso | eng |
dc.relation | http://www.sciencedirect.com/science/article/pii/S1569190X14000434 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture |
dc.subject | Multiprocessors |
dc.subject | Cache coherence protocol |
dc.subject | Gem5 |
dc.subject | Multicore |
dc.subject | Network-on-chip |
dc.subject | Prefetching |
dc.subject | Simulation infrastructure |
dc.subject | Arquitectura d'ordinadors |
dc.subject | Multiprocessadors |
dc.title | Network aware performance evaluation of prefetching techniques in CMPs |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
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