Improving The Robustness Of The Register File: a Register File Cache Architecture

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Canal Corretger, Ramon
dc.contributor.author	Zhuang, Sicong
dc.date	2014-09-09
dc.identifier.citation	102852
dc.identifier.uri	http://hdl.handle.net/2099.1/22656
dc.language.iso	eng
dc.publisher	Universitat Politècnica de Catalunya
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Microprocessors
dc.subject	register file
dc.subject	process variation
dc.subject	soft error
dc.subject	register file
dc.subject	process variation
dc.subject	soft error
dc.subject	Microprocessadors
dc.title	Improving The Robustness Of The Register File: a Register File Cache Architecture
dc.type	info:eu-repo/semantics/masterThesis
dc.description.abstract	This thesis exploits a multi-band cache-like register file architecture to mitigate the potential damage caused by process variations and soft error (single event upsets). An quantitative analysis is conducted to measure the possible gains and loses by incorporating it using simulation results.

Zhuang, Sicong; Casas, Marc

Pietri, Ilia; Zhuang, Sicong; Casas, Marc; Moretó, Miquel; Sakellariou, Rizos

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