Transactional memory: an overview

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/28410

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	Harris, T
dc.contributor.author	Cristal Kestelman, Adrián
dc.contributor.author	Unsal, Osman Sabri
dc.contributor.author	Ayguadé Parra, Eduard
dc.contributor.author	Gagliardi, F
dc.contributor.author	Smith, B
dc.contributor.author	Valero Cortés, Mateo
dc.date	2007-05
dc.identifier.citation	Harris, T. [et al.]. Transactional memory: an overview. "IEEE micro", Maig 2007, vol. 27, núm. 3, p. 8-29.
dc.identifier.citation	0272-1732
dc.identifier.citation	10.1109/MM.2007.63
dc.identifier.uri	http://hdl.handle.net/2117/28410
dc.language.iso	eng
dc.relation	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4292053&tag=1
dc.rights	Attribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject	Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject	Memory management (Computer science)
dc.subject	Parallel programming (Computer science)
dc.subject	Distributed shared memory systems
dc.subject	Parallel programming
dc.subject	Storage management
dc.subject	Gestió de memòria (Informàtica)
dc.subject	Programació en paral·lel (Informàtica)
dc.title	Transactional memory: an overview
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	Writing applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ones. This article presents a survey of transactional memory, a mechanism that promises to enable scalable performance while freeing programmers from some of the burden of modifying their parallel code.
dc.description.abstract	Peer Reviewed

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