To access the full text documents, please follow this link: http://hdl.handle.net/2117/91144
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Aleta Ortega, Alexandre |
dc.contributor.author | Codina Viñas, Josep M. |
dc.contributor.author | Sánchez Navarro, F. Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Kaeli, D |
dc.date | 2009-06 |
dc.identifier.citation | Aleta, A., Codina, J.M., Sánchez, F., González, A., Kaeli, D. AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures. "IEEE transactions on computers", Juny 2009, vol. 58, núm. 6, p. 770-783. |
dc.identifier.citation | 0018-9340 |
dc.identifier.citation | 10.1109/TC.2009.32 |
dc.identifier.uri | http://hdl.handle.net/2117/91144 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4785457 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Graph theory |
dc.subject | Clustered microarchitectures |
dc.subject | ILP |
dc.subject | Instruction replication |
dc.subject | Modulo scheduling |
dc.subject | Statically scheduled processors |
dc.subject | Microprocessadors |
dc.subject | Grafs, Teoria de |
dc.title | AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |