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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Marcuello, Pedro |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.date | 2004-02 |
dc.identifier.citation | Marcuello, P., Gonzalez, A., Tubella, J. Thread partitioning and value prediction for exploiting speculative thread-level parallelism. "IEEE transactions on computers", Febrer 2004, vol. 53, núm. 2, p. 114-125. |
dc.identifier.citation | 0018-9340 |
dc.identifier.citation | 10.1109/TC.2004.1261823 |
dc.identifier.uri | http://hdl.handle.net/2117/101437 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/document/1261823/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Compilers (Computer programs) |
dc.subject | Speculative thread-level parallelism |
dc.subject | Value prediction |
dc.subject | Branch prediction |
dc.subject | Thread spawning policies |
dc.subject | Clustered architectures |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Compiladors (Programes d'ordinador) |
dc.title | Thread partitioning and value prediction for exploiting speculative thread-level parallelism |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |