Dynamic cluster resizing

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/102496

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.author	González González, José
dc.contributor.author	González Colás, Antonio María
dc.date	2003
dc.identifier.citation	González, J., Gonzalez, A. Dynamic cluster resizing. A: IEEE International Conference on Computer Design. "Proceedings 21st International Conference on Computer Design". San Jose, California: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 375-377.
dc.identifier.citation	0-7695-2025-1
dc.identifier.citation	10.1109/ICCD.2003.1240922
dc.identifier.uri	http://hdl.handle.net/2117/102496
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	http://ieeexplore.ieee.org/document/1240922/
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Microprocessors -- Energy consumption
dc.subject	Computer architecture
dc.subject	Queueing theory
dc.subject	Resource allocation
dc.subject	Statistical analysis
dc.subject	Microprocessadors -- Consum d'energia
dc.title	Dynamic cluster resizing
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	Processor resources required for an effective execution of an application vary across different sections. We propose to take advantage of clustering to turn-off resources that do not contribute to improve performance. First, we present a simple hardware scheme to dynamically compute the energy consumed by each processor block and the energy-delay2 product for a given interval of time. This scheme is used to compute the effectiveness of the current configuration in terms of energy-delay2 and evaluate the benefits of increasing/decreasing the number of active issue queues. Performance evaluation shows an average energy-delay2 product improvement of 18%, and up to 50% for some applications, in a quad-cluster architecture.
dc.description.abstract	Peer Reviewed

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