To access the full text documents, please follow this link: http://hdl.handle.net/2117/105273
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.contributor.author | Molina, Carlos |
dc.date | 1999 |
dc.identifier.citation | González, A., Tubella, J., Molina, C. Trace-level reuse. A: International Conference on Parallel Processing. "1999 InternationaI Conference on Parallel Processing: 21-24 September 1999, Aizu-Wakamatsu City, Japan: proceedings". Aizu-Wakamatsu: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 30-37. |
dc.identifier.citation | 0-7695-0350-0 |
dc.identifier.citation | 10.1109/ICPP.1999.797385 |
dc.identifier.uri | http://hdl.handle.net/2117/105273 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/797385/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Performance evaluation |
dc.subject | Multiprocessing systems |
dc.subject | Instruction sets |
dc.subject | Resource allocation |
dc.subject | Microprocessadors |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Trace-level reuse |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |