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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Espasa Sans, Roger |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 1997 |
dc.identifier.citation | Espasa, R., Valero, M. Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. A: International Conference on High-Performance Computing. "Fourth International Conference on High-Performance Computing: December 18-21, 1997, Bangalore, India: proceedings". Bangalore: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 350-357. |
dc.identifier.citation | 0-8186-8067-9 |
dc.identifier.citation | 10.1109/HIPC.1997.634514 |
dc.identifier.uri | http://hdl.handle.net/2117/108432 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/634514/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Performance evaluation |
dc.subject | Vector processor systems |
dc.subject | Parallel architectures |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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