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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Servat, Harald |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Hoppe, Hans-Christian |
dc.contributor.author | Gimenez, Judit |
dc.contributor.author | Peña, Antonio J. |
dc.date | 2017 |
dc.identifier.citation | Servat, H., Labarta, J., Hoppe, H., Gimenez, J., Peña, A. Integrating memory perspective into the BSC performance tools. A: International Conference on Parallel Processing Workshops. "ICPPW 2017: 46th International Conference on Parallel Processing Workshops: 14 August 2017, Bristol, United Kingdom: proceedings". Bristol: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 231-232. |
dc.identifier.citation | 978-1-5386-1044-2 |
dc.identifier.citation | 10.1109/ICPPW.2017.42 |
dc.identifier.uri | http://hdl.handle.net/2117/109834 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/8026090/ |
dc.relation | info:eu-repo/grantAgreement/ES/PE2013-2016/IJCI-2015-23266 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Tools |
dc.subject | Benchmark testing |
dc.subject | Instruments |
dc.subject | Resource management |
dc.subject | Parallel processing |
dc.subject | Performance analysis |
dc.subject | Memory references |
dc.subject | Sampling |
dc.subject | Instrumentation |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Integrating memory perspective into the BSC performance tools |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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