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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Larriba Pey, Josep |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2000 |
dc.identifier.citation | Ramírez, A., Larriba, J., Valero, M. Trace cache redundancy: red and blue traces. A: International Symposium on High-Performance Computer Architecture. "Sixth International Symposium on High-Performance Computer Architecture, HPCA-6: January 8-12, 2000, Toulouse, France: proceedings". Toulouse: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 325-333. |
dc.identifier.citation | 0-7695-0550-3 |
dc.identifier.citation | 10.1109/HPCA.2000.824361 |
dc.identifier.uri | http://hdl.handle.net/2117/112118 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/824361/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Cache memory |
dc.subject | Redundancy |
dc.subject | Parallel processing |
dc.subject | Performance evaluation |
dc.subject | Cache storage |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Trace cache redundancy: red and blue traces |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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