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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Gonzalez Martin, Isidro |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Veindenbaum, Alex |
dc.contributor.author | Ramírez, Marco Antonio |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2008-09 |
dc.identifier.citation | González, I., Cristal, A., Veindenbaum, A., Ramírez, M., Valero, M. "The MS-processor's register file timing and power evaluation". 2008. |
dc.identifier.uri | http://hdl.handle.net/2117/112392 |
dc.language.iso | eng |
dc.relation | UPC-DAC-RR-CAP-2008-24 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Logic design |
dc.subject | Chip architectures |
dc.subject | Multi-State Processor’s RF design |
dc.subject | SPICE simulator |
dc.subject | Power consumption |
dc.subject | Predictive technology models |
dc.subject | PMT |
dc.subject | Microprocessadors -- Consum d'energia |
dc.subject | Estructura lògica |
dc.title | The MS-processor's register file timing and power evaluation |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/report |
dc.description.abstract |