Second order sigma-delta control of charge trapping for MOS capacitors

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dc.contributor	Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
dc.contributor.author	Bheesayagari, Chenna Reddy
dc.contributor.author	Gorreta Mariné, Sergio
dc.contributor.author	Pons Nin, Joan
dc.contributor.author	Domínguez Pumar, Manuel
dc.date	2017-09-01
dc.identifier.citation	Bheesayagari, C., Gorreta, S., Pons, J., Dominguez, M. Second order sigma-delta control of charge trapping for MOS capacitors. "Microelectronics reliability", 1 Setembre 2017, vol. 76-77, p. 635-639.
dc.identifier.citation	0026-2714
dc.identifier.citation	10.1016/j.microrel.2017.06.096
dc.identifier.uri	http://hdl.handle.net/2117/115875
dc.language.iso	eng
dc.relation	http://www.sciencedirect.com/science/article/pii/S0026271417302846?via%3Dihub
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica
dc.subject	Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal
dc.subject	Dielectric devices
dc.subject	Charge trapping
dc.subject	MOS
dc.subject	Dielectric charging
dc.subject	Sigma-delta
dc.subject	Sliding mode control
dc.subject	Dispositius dielèctrics
dc.title	Second order sigma-delta control of charge trapping for MOS capacitors
dc.type	info:eu-repo/semantics/submittedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	This paper presents the circuit topology of a second order sigma-delta control of charge trapping for MOS capacitors. With this new topology it is possible to avoid the presence of plateaus that can be found in first-order sigma-delta modulators. Plateaus are unwanted phenomena in which the control is locked for a certain time interval (of unknown duration). In this case the control output is constant and therefore the controlled device is in fact in open-loop configuration. It is shown that the presence of plateaus is avoided in MOS capacitors using the proposed approach.
dc.description.abstract	Peer Reviewed

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