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dc.contributor | Barcelona Supercomputing Center |
---|---|
dc.contributor.author | Cazorla, Francisco J. |
dc.contributor.author | Abella, Jaume |
dc.contributor.author | Mezzetti, Enrico |
dc.contributor.author | Hernandez, Carles |
dc.contributor.author | Vardanega, Tullio |
dc.contributor.author | Bernat, Guillem |
dc.date | 2018-04 |
dc.identifier.citation | Cazorla, F. J. [et al.]. Reconciling Time Predictability and Performance in Future Computing Systems. "IEEE Design & Test", Abril 2018, vol. 35, núm. 2, p. 48-56. |
dc.identifier.citation | 2168-2356 |
dc.identifier.citation | 10.1109/MDAT.2017.2766558 |
dc.identifier.uri | http://hdl.handle.net/2117/115861 |
dc.language.iso | eng |
dc.publisher | IEEE |
dc.relation | http://ieeexplore.ieee.org./document/8082514/ |
dc.relation | info:eu-repo/grantAgreement/MIENCO/PE2013-2016/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/MIENCO/PE2013-2016/TIN2014-60404-JIN |
dc.relation | info:eu-repo/grantAgreement/ES/PE2013-2016/RYC-2013-14717 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | High performance computing |
dc.subject | Computer architecture |
dc.subject | C.3.d Real-time and embedded systems |
dc.subject | C.0.d Modeling of computer architecture |
dc.subject | Hardware |
dc.subject | Time factors |
dc.subject | Monitoring |
dc.subject | Hardware design languages |
dc.subject | Supercomputadors |
dc.subject | Arquitectura d'ordinadors |
dc.title | Reconciling Time Predictability and Performance in Future Computing Systems |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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