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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
dc.contributor.author | Liang, Xiaoyao |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Wei, Gu-Yeon |
dc.date | 2008-02 |
dc.identifier.citation | Liang, X., Canal, R., Wei, G.-Y. Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability. "IEEE micro", Febrer 2008, vol. 28, núm. 1, p. 60-68. |
dc.identifier.citation | 0272-1732 |
dc.identifier.citation | 10.1109/MM.2008.12 |
dc.identifier.uri | http://hdl.handle.net/2117/121204 |
dc.language.iso | eng |
dc.relation | https://ieeexplore.ieee.org/document/4460513/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Memory management (Computer science) |
dc.subject | Microprocessors |
dc.subject | Cache memory |
dc.subject | Cache storage |
dc.subject | DRAM chips |
dc.subject | Microprocessor chips |
dc.subject | SRAM chips |
dc.subject | System-on-chip |
dc.subject | Transistors |
dc.subject | Gestió de memòria (Informàtica) |
dc.subject | Microprocessadors |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
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