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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Aleta Ortega, Alexandre |
dc.contributor.author | Codina, Josep Maria |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Kaeli, David |
dc.date | 2007 |
dc.identifier.citation | Aleta, A., Codina, J., González, A., Kaeli, D. Heterogeneous clustered VLIW microarchitectures. A: International Symposium on Code Generation and Optimization. "International Symposium on Code Generation and Optimization, CGO 2007: 11-14 March 2007, San Jose, California". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 354-366. |
dc.identifier.citation | 978-0-7695-2764-2 |
dc.identifier.citation | 10.1109/CGO.2007.15 |
dc.identifier.uri | http://hdl.handle.net/2117/96796 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/4145127/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | VLIW |
dc.subject | Microarchitecture |
dc.subject | Frequency |
dc.subject | Voltage |
dc.subject | Energy consumption |
dc.subject | Processor scheduling |
dc.subject | Delay |
dc.subject | Multiprocessor interconnection networks |
dc.subject | Microprocessadors |
dc.title | Heterogeneous clustered VLIW microarchitectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |