Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/11974
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Vega, Augusto |
dc.contributor.author | Rico Carro, Alejandro |
dc.contributor.author | Cabarcas, Felipe |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2010 |
dc.identifier.citation | Vega, A. [et al.]. Comparing last-level cache designs for CMP architectures. A: International Forum on Next Generation Multicore/Manycore Tecnologies. "2nd International Forum on Next Generation Multicore/Manycore Tecnologies". Saint-Malo: 2010, p. 1-11. |
dc.identifier.citation | 978-1-4503-0008-7 |
dc.identifier.citation | 10.1145/1882453.1882456 |
dc.identifier.uri | http://hdl.handle.net/2117/11974 |
dc.language.iso | eng |
dc.relation | http://portal.acm.org/citation.cfm?id=1882453.1882456&coll=DL&dl=GUIDE&CFID=13095133&CFTOKEN=13920290 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/248647/EU/ENabling technologies for a programmable many-CORE/ENCORE |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture -- Analysis |
dc.subject | Multiple data stream architectures |
dc.subject | Chip-multiprocessor |
dc.subject | Cache sharing |
dc.subject | Non-uniform cache architecture |
dc.subject | Arquitectura de computadors |
dc.title | Comparing last-level cache designs for CMP architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |