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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.date | 2013-08-15 |
dc.identifier.citation | Gomez, S.; Moll, F. Yield estimation model for lithography hotspot distortions. "Electronics Letters", 15 Agost 2013, vol. 49, núm. 17, p. 1066-1068. |
dc.identifier.citation | 0013-5194 |
dc.identifier.citation | 10.1049/el.2013.0469 |
dc.identifier.uri | http://hdl.handle.net/2117/20390 |
dc.language.iso | eng |
dc.publisher | Institution of Electrical Engineers |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6583109 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Àrees temàtiques de la UPC::Enginyeria dels materials |
dc.subject | Hot spot |
dc.subject | Manufacturing yield |
dc.subject | Yield estimation |
dc.subject | Yield loss |
dc.subject | Yield modeling |
dc.subject | Litografia per feix d'electrons |
dc.subject | Litografia |
dc.title | Yield estimation model for lithography hotspot distortions |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract |