Measurements of process variability in 40-nm regular and nonregular layouts

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Title:	Measurements of process variability in 40-nm regular and nonregular layouts
Author:	Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Abstract:	As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors -Lithography distortion -Variability -Fluctuations -Mosfets -Circuits integrats -Integrated circuits
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Article
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