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Title:	Logic synthesis for manufacturability considering regularity and lithography printability
Author:	Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Abstract:	This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different levels of regularity and different area overheads during the logic synthesis, in order to improve overall design yield. A technology remapping tool with such yield model as cost function is proposed and implemented and interesting results are presented.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Integrated circuits -Lithography -Design for manufacture -Integrated circuit layout -Lithography -IC layout -Integrated circuit manufacturing -Lithography printability -Logic synthesis -technology remapping tool -Yield loss -Cost function -Integrated circuit modeling -Layout -Libraries -Lithography -Semiconductor device modeling -Superluminescent diodes -Lithography -Regularity -Technology mapping -Yield model -Circuits integrats -Litografia
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Conference Object
Published by:	IEEE Computer Society Publications
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