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Modelling bus contention during system early design stages
Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J.
Barcelona Supercomputing Center
-Àrees temàtiques de la UPC::Enginyeria elèctrica
-High performance computing
-Mathematical modelling
-Multicore processing
-Timing
-Program processors
-Load modeling
-Mathematical model
-Schedules
-Analytical models
-Multiprocessing systems
-Real-time systems
-Resource allocation
-System buses
-Supercomputadors
-Matemàtica--Investigació
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Article - Submitted version
Conference Object
IEEE
         

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