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Title: | Modelling bus contention during system early design stages |
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Author: | Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. |
Other authors: | Barcelona Supercomputing Center |
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Subject(s): | -Àrees temàtiques de la UPC::Enginyeria elèctrica -High performance computing -Mathematical modelling -Multicore processing -Timing -Program processors -Load modeling -Mathematical model -Schedules -Analytical models -Multiprocessing systems -Real-time systems -Resource allocation -System buses -Supercomputadors -Matemàtica--Investigació |
Rights: | Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
Document type: | Article - Submitted version Conference Object |
Published by: | IEEE |
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