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Título:
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High-level synthesis techniques for reducing the activity of functional units
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Autor/a:
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Musoll Cinca, Enric; Cortadella, Jordi
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Otros autores:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
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Abstract:
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Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Digital integrated circuits
-Electronic circuit design
-Logic design
-High-level synthesis
-Functional units
-Low power
-Switch-level simulations
-Design process
-Circuits integrats digitals
-Circuits electrònics -- Disseny i construcció
-Estructura lògica |
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Derechos:
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Tipo de documento:
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Artículo - Versión publicada
Objeto de conferencia |
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Editor:
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Association for Computing Machinery (ACM)
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Compartir:
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