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Título:
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Optimizing CMOS circuits for low power using transistor reordering
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Autor/a:
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Musoll Cinca, Enric; Cortadella, Jordi
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Otros autores:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
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Abstract:
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This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. This power consumption depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by recording its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Logic circuits
-Electronic circuit design
-CMOS logic circuits
-Circuit optimisation
-Combinational circuits
-Circuit CAD
-Logic CAD
-Stochastic processes
-Multivalued logic circuits
-Circuits electrònics -- Disseny i construcció
-Circuits lògics |
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Derechos:
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Tipo de documento:
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Artículo - Versión publicada
Objeto de conferencia |
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Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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Compartir:
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