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Título:
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Verification of asynchronous circuits by BDD-based model checking of Petri nets
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Autor/a:
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Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric
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Otros autores:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
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Abstract:
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This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification and the gate-level network behavior by means of boolean functions. These functions are efficiently handled by using Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, the applicability of our verification method has been proven by checking the correctness of different benchmarks. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Asynchronous circuits
-Petri nets
-Logic circuits
-Model check
-Boolean function
-Excitation function
-Binary decision diagram
-Symbolic model check
-Circuits asíncrons
-Petri, Xarxes de
-Circuits lògics |
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Derechos:
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Tipo de documento:
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Artículo - Versión presentada
Objeto de conferencia |
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Editor:
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Springer
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Compartir:
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