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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Sazeides, Yanos |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2011 |
dc.identifier.citation | Abella, J. [et al.]. RVC: A mechanism for time-analyzable real-time processors with faulty caches. A: International Conference on High Performance Embedded Architectures & Compilers (HiPEAC). "6th International Conference on High Performance and Embedded Architectures and Compilers". 2011, p. 97-106. |
dc.identifier.citation | 978-145030241-8 |
dc.identifier.citation | 10.1145/1944862.1944878 |
dc.identifier.uri | http://hdl.handle.net/2117/13178 |
dc.language.iso | eng |
dc.relation | http://dl.acm.org/citation.cfm?id=1944878 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject | Hardware -- Reliability |
dc.subject | Real time |
dc.subject | Time analysis |
dc.subject | Computadors -- Fiabilitat |
dc.title | RVC: A mechanism for time-analyzable real-time processors with faulty caches |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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