Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/20001
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | García Leyva, Lancelot |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2013 |
dc.identifier.citation | García, L. [et al.]. Novel redundant logic design for noisy low voltage scenarios. A: Latin American Symposium on Circuits and Systems. "LASCAS 2013 - Proceedings of 4th Latin American Symposium on Circuits and Systems". Cusco: 2013, p. 1-4. |
dc.identifier.citation | 10.1109/LASCAS.2013.6519010 |
dc.identifier.uri | http://hdl.handle.net/2117/20001 |
dc.language.iso | eng |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Integrated circuits |
dc.subject | AWGN |
dc.subject | CMOS logic circuits |
dc.subject | integrated circuit reliability |
dc.subject | logic design |
dc.subject | logic gates |
dc.subject | Circuits integrats |
dc.subject | AWGN |
dc.subject | CMOS logic circuits |
dc.subject | integrated circuit reliability |
dc.subject | logic design |
dc.title | Novel redundant logic design for noisy low voltage scenarios |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |