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dc.contributor | Villardi de Montlaur, Adeline de |
---|---|
dc.contributor | Ghoraishi, Mir |
dc.contributor.author | Arteaga Martinez, Xavier |
dc.date | 2015-05-15 |
dc.identifier.uri | http://hdl.handle.net/2099.1/26604 |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | FPGA |
dc.subject | Programmable logic devices |
dc.subject | Software Defined Radio SDR |
dc.subject | Filter Bank Multicarrier |
dc.subject | FPGA hardware prototyping co-simulation OFDM 5G |
dc.subject | Dispositius lògics programables |
dc.subject | Convertidors analògic/digitals |
dc.title | Prototyping FBMC/OQAM for 5G mobile communications proof of concept |
dc.type | info:eu-repo/semantics/masterThesis |
dc.description.abstract |