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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Hernández, Carles |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Gianarro, Andrea |
dc.contributor.author | Andersson, Jan |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.date | 2016 |
dc.identifier.citation | Hernández, C., Abella, J., Gianarro, A., Andersson, J., Cazorla, F. Random Modulo: A new processor cache design for real-time critical systems. A: Design Automation Conference. "Proceedings of the 2016 53rd ACM/EDAC/IEEE Design Automation Conference (DAC)". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-6. |
dc.identifier.citation | 978-1-4673-8729-3 |
dc.identifier.citation | 10.1145/2897937.2898076 |
dc.identifier.uri | http://hdl.handle.net/2117/99585 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/abstract/document/7544273/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2014-60404-JIN |
dc.relation | info:eu-repo/grantAgreement/ES/RYC-2013-14717 |
dc.relation | info:eu-repo/grantAgreement/ES/RYC-2013-14717 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2014-60404-JIN |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Cache memory |
dc.subject | Cache memories |
dc.subject | Measurement-Based Probabilistic Timing Analysis (MBPTA) |
dc.subject | Random Modulo (RM) |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Random Modulo: A new processor cache design for real-time critical systems |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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